Dual Issue
Dual issue is when the CPU starts two (or more) instructions in the same clock cycle because they don’t conflict with each other.
Why?
A pipelined CPU issues one instruction per cycle — but if the hardware has spare fetch/decode bandwidth and multiple functional units sitting idle, that’s wasted capacity. If the next instruction has nothing to do with the current one, there’s no reason to make it wait a cycle; start both at once and double throughput for free.
Two instructions can dual-issue when they:
- Take about the same amount of time
- Use unrelated registers (no data dependency)
- Don’t consume two of the same resource (e.g. not both floating-point)
- Can be fed by the available fetch/decode units
ADD R1, 16 ┐
CMP R2, 0 ┘ different registers, different units → both start cycle N
Why a programmer might care. In a tight compute loop (e.g. media encode/decode), arranging independent instructions next to each other guarantees dual issue every cycle. If consecutive instructions share a register or resource, the second one has to wait — and you lose the slot. On an embedded target with a predictable pipeline, you can hand-schedule for this.