Instruction-Level Parallelism (ILP)
Instruction-Level Parallelism is the set of hardware techniques that let a CPU do more work per clock cycle by overlapping or reordering instructions, rather than raising the clock.
Why?
Clock speeds hit the ~3 GHz power wall around 2005. The remaining way to run programs faster is to squeeze more useful work out of each cycle, so ILP became central.
ILP itself is now one of the remaining walls: branch prediction is already at ~95% accuracy, so further gains are small. First seen in ECE222 via 8 Great Ideas in Computer Architecture.
Techniques:
- Pipelining
- Pipeline Hazard
- Miss Shadow
- Branch Prediction
- Speculative Execution
- Dual Issue
- Register Renaming
- Out-of-Order Execution
These are synergistic, not independent; L06 presents them as a group where “each adds to the benefits the other brings.” The whole point of the group is hiding memory latency.
Intel’s Itanium bet on static (compile-time) parallelism and lost; x86 won with dynamic (run-time) parallelism.
Resources