MSI Protocol
Write-Through Protocol, where we have 2 states: valid and invalid. The cache is invalidated whenever a write is done.
However, we can be slightly more efficient by using 3 states instead of 2 (called write-back protocol (MSI)). We can just indicate that our data has been changed but not yet been written to memory. Only when another core is needed do we actually write to memory.
We have 3 states:
- Modified—only this cache has a valid copy; main memory is out-of-date.
- Shared—location is unmodified, up-to-date with main memory; may be present in other caches (also up-to-date).
- Invalid
The initial state for a memory location, upon its first read, is “shared”. The implementation will only write the data to memory if another processor requests it. During write-back, a processor may read the data from the bus.
An Extension to MSI: MESI
The most common protocol for cache coherence is MESI. This protocol adds yet another state:
- Modified—only this cache has a valid copy; main memory is out-of-date.
- Exclusive—only this cache has a valid copy; main memory is up-to-date.
- Shared—same as before.
- Invalid—same as before
MESI allows a processor to modify data exclusive to it, without having to communicate with the bus. MESI is safe. The key is that if memory is in the E state, no other processor has the data. The transition from E to M does not have to be reported over the bus, which potentially saves some work and reduces bus usage.
MESIF
MESIF Used in latest i7 processors. We introduce another state:
- Forward—basically a shared state; but, current cache is the only one that will respond to a request to transfer the data
Hence: a processor requesting data that is already shared or exclusive will only get one response transferring the data. Under a more simple MESI scheme you could get multiple caches trying to answer, with leads to bus arbitration or contention. The existence of a F state permits more efficient usage of the bus.