Write-Back Cache

MSI Protocol

The simplest write-back cache-coherence protocol. Uses 3 states per cached line instead of the 2 (Valid/Invalid) from write-through.

By tracking whether the line is dirty, we avoid flushing to memory on every write; the flush only happens when another processor asks for the data.

Why?

Write-through pushes every store to memory, wasting bandwidth when the same line is written repeatedly. MSI lets a core hoard a dirty copy locally and only pay the memory round-trip when coherence forces it.

States:

• Modified: only this cache has a valid copy; main memory is out of date
• Shared: unmodified and up to date with main memory; may also live in other caches
• Invalid: not valid

Initial state on first read is Shared. A Modified line is written back when another processor requests it, and the requester can read the value off the bus during write-back.

State Machine

Bus actions: BusRd (read), BusRdX (exclusive read / read-to-own), BusWB (write-back / flush).

Columns: Observed is the event this cache just saw; Generated is the message (if any) this cache broadcasts on the bus in response. Blank = silent.

State	Observed	Generated	Next State
Modified	PrRd		Modified
Modified	PrWr		Modified
Modified	BusRd	BusWB	Shared
Modified	BusRdX	BusWB	Invalid
Shared	PrRd		Shared
Shared	BusRd		Shared
Shared	BusRdX		Invalid
Shared	PrWr	BusRdX	Modified
Invalid	PrRd	BusRd	Shared
Invalid	PrWr	BusRdX	Modified

Example

Initially x = 7 in main memory.

1. CPU1 reads x from memory (BusRd, Shared)
2. CPU3 reads x from memory (BusRd, Shared)
3. CPU3 writes x := 42 (PrWr from Shared): generates BusRdX, CPU1 snoops and invalidates its copy; CPU3 transitions to Modified
4. CPU1 reads x (PrRd from Invalid): generates BusRd; CPU3 writes back the value and drops to Shared; CPU1 reads 42 off the bus as Shared
5. CPU2 reads x from memory (BusRd, Shared)

MESI extends this with an Exclusive state so a clean, single-owner line can be upgraded to Modified without bus traffic.

Related

• Write-Back Cache
• Write-Through Cache
• MESI Protocol
• Cache Coherency