ECE222: Digital Computers
I needed to convince myself that this course is useful. It is extremely useful, because software oftentimes need to interact with hardware. When you run out of Memory, or you see the term DDR4 and you never understood what it stood for, and now you finally do! Or the idea of Cache Coherency! You are going to learn it all within a week, this is super exciting.
Link to course notes here.
101001110011000001011101010 1 11 10
Tag | Index (1 bit) | Word Offset (2 bits) | Byte Offset (2 bits)
They call the word offset -> block offset??
- Makes more sense to call it word offset
No, actually read the book Chapter 4 starts at page 335 Chapter 5 starts at page 525
- When accessing the array, always assume Double Word??
- Practice writing the binary, especially for these weird ones UJ, U-type instructions where you need to combine immediate with a number of 0 bits
- Understand how you can convert from a C program to actually RISC-V commands, especially important is passing the parameters
TODO: Practice doing the lookup table with the Multi-Level Page Table. It’s super important that it sticks in your head.
- Question 2, I still can’t do it???
Final Exam: Branch happens at ID, which is why you need a NOP.
I always get question 8 wrong
- NOOOO Basically, for the old instruction, use the total number of clock cycles that they give to you, and then count the other one, to get you the clock cycles for that instruction
- Do CPI / (CPI - percentage in decimal that the instruction we are removing is taking)
Review starting page 30 about the performance calculations, benchmarking, etc.
- This is actually pretty interesting, I would have done this if I were to go to AMD Chapter 2
QUIZ: Question 1, ahh you need to worry about the signed integer number.
- I need to learn how to count the number of instructions properly
- BEQ: We add an 0 bit at the end, always make sure to check the green card
- jump = (text size) - (line # of jal instruction) = 384 - 24 = 360
(Optional) This is super interesting, x86 architecture Chapter 4
Main thing is drawing the diagram from scratch, being able to do that shows that you really understand
understand how the diagrams in Control Unit is implemented. How the different control lines are set depending on the instruction is pretty important
Multicycle stuff chapter 4.4?? I haven’t really spent the time trying to understand that
Pipelining, you really need to understand that stuff Chapter 5
Sometimes, words are 64 bits, sometimes 32 bits, you need to be very careful
- total bits = # of blocks * (# bits for tag + # bits to store data in block + 1)
5.5.6 how did they get that answer???
Review 5.7 -> Basically read has three parts, instruction miss, data read miss, and write-allocate
- This is taking so much time, I will review this if I have time
I thought I understood at a high level how memory worked, but when it came time to seeing the actual things and figuring out if there was a cache miss, I had trouble. Like the process of doing it yourself was hard
I don’t understand well how cache miss, and read works
I didn’t look into Virtual Memory enough
I didn’t look into the 5.16 fallacies and pitfalls, and conclusion
(Optional) The history, 5.18 is also pretty interesting. They teach you about the history of memory and Database
Watch this playlist instead of going to class: https://www.youtube.com/watch?v=z_2mJ83a0_k&list=PLJJfglnfh3lS2GrxNFffv9sgcC192TvWr
Chapter Exams notes
- QUIZ: Question 1?? I get 64, not 60. How did they get 60??
- It’s because one of the bits is permanently 0. So instead of adding 31, they actually add another value.
- Pipeline time improvement: Take the maximum from before, and then merge the two adjacent such that it produces the minimum sum, and then subtract the delay.
- The MemToReg value can be X, since you are setting RegWrite to 0. So whatever value you set to write doesn’t matter at all.
Chapter 5 common page table size is 4KB
word addressable, always no offset or??
- This n-way thing is insanely hard, damn https://piazza.com/class/l7rm65q9rgn2rz/post/439
- So basically, there are n-ways, and each way has a certain amount of blocks
- The blocks are numbered in reverse order, because Little Endian ahh!
- So ex:
block 3 | block 2 | block 1 | block 0Each way has a certain size
- So ex:
Now, when you index, you still index into the block, but then there are multiple ways, also see slides again it’s Tag | Index | Offset
- The number of levels of the multilevel page table required:
- Moore’s Law
- ENIAC was a general purpose machine.
- 8 Great Ideas in Computer Architecture
- Computer Memory
- Comparing performance using Performance Test
- CPU for execution time
- CPU Performance
- Amdahl’s Law
- Program Counter
- Liquid Crystal Display
- Local Area Network
- Wide Area Network
- Electromagnetic Induction
- Byte Addressing
- Instruction Set Architecture
- Computer Memory
- Alignment Restriction
- Dynamically Linked Libraries (DLLs)
- RISC-V Implementation
- State Element
- Control Unit
- Edge-Triggered Clocking
- Clock Signal
- Arithmetic Logic Unit (ALU)
- Dealing with the 3 kinds of hazards
- Vectored Interrupt
- Memory-Mapped IO
Chapter 5: Computer Memory
- Memory Hierarchy
- Principle of Locality
- Hit Rate
- Flash Memory
- Wear Leveling
- Disk Memory
- LRU Scheme
- Cache Performance
- Content-Addressable Memory
- Write Buffer
- Hamming Distance
- Error Detection and Correction
- Error Correction Code
- Virtual Machine
- Virtual Memory
- Segmentation (Memory)
- Translation-Lookaside Buffer (TLB)
- Data Striping
- Redundant Array of Inexpensive Disks (RAID)
Chapter 6 (self-study)
1 word = 4 bytes = 32 bits double-word = 8 bytes = 64 bits
Computer Program -> REALLY IMPORTANT PAGE TO UNDERSTAND THE DIFFERENT LAYERS OF THE COMPUTER PROGRAM
Chapter 4: Review
- Convert hex to binary