MESI Protocol
The most common cache-coherence protocol. MESI extends the 3-state MSI write-back protocol with an Exclusive state.
Why add E?
Under plain MSI, a line read by only one core still starts in Shared, so the first write has to broadcast a
BusRdXto invalidate others, even though nobody else holds it.MESI detects “I’m the only one” at read time and lets a Exclusive→Modified transition without notifying the bus.
States
- Modified: only this cache has a valid copy; main memory is out of date
- Exclusive: only this cache has a valid copy; main memory is up to date
- Shared: unmodified, may be present in other caches, all up to date
- Invalid: not valid
The E→M transition is local and does not appear on the bus, which saves work and reduces bus traffic. This is safe precisely because E means no other processor has the line.
MESIF
Used in recent Intel processors. Adds a fifth state:
- Forward: a Shared-like state, but the forwarding cache is the only one that will respond to a bus request for that line
Under plain MESI, multiple caches holding a Shared line may all try to answer a BusRd, triggering bus arbitration. MESIF designates a single responder, so a processor requesting an already-shared or -exclusive line gets exactly one response.