Write-Back Cache
A cache-coherence strategy that delays flushing writes to main memory for as long as possible, so repeated writes to the same line coalesce into a single memory round-trip.
Why?
If CPU3 writes
xthree times in rapid succession under write-through, we flush three times. Write-back flushes once (on eviction or when another core asks for the line), trading memory bandwidth for a bit of protocol complexity.
Where "write-back" comes from
The write stops at the cache and is sent back to main memory later (on eviction, or when another core demands it). The “back” is temporal, not directional.
Requires a dirty bit in hardware to mark lines changed-but-not-yet-flushed, plus snooping so other caches know when to request a flush before reading a line another core has modified.
Concrete write-back implementations differ by how many states each cached line tracks:
- MSI: 3 states (Modified / Shared / Invalid); simplest
- MESI: adds Exclusive; most common in real CPUs
- MESIF: adds Forward; used in recent Intel CPUs
Difference with Write-Through Cache?
Write-through pushes every store to memory with just 2 states (Valid / Invalid), simpler but no coalescing. Write-back keeps writes local in M state, needs 3+ states and more bus machinery, but slashes memory traffic on write-heavy workloads.