Cache Coherency

Write-Through Cache

The simplest write policy for a coherent cache (vs write-back):

• All cache writes go to main memory
• All cache writes appear on the bus
• Other CPUs snoop; if they have the same location cached they either invalidate or update

Where "write-through" comes from

The write passes through the cache straight to main memory. The cache is a pit stop, not the destination.

Invalidation is the most common protocol. Invalid + x = 42; can bypass the cache and go straight to memory (write no-allocate) since the previous value doesn’t matter.

State Machine

Two states per cached line: Valid / Invalid. Events come from the processor (Pr) or the bus (Bus); actions are Rd (read) or Wr (write).

Columns: Observed is the event this cache just saw; Generated is the message (if any) this cache broadcasts on the bus in response, so other caches can react. Blank = silent.

State	Observed	Generated	Next State
Valid	PrRd		Valid
Valid	PrWr	BusWr	Valid
Valid	BusWr		Invalid
Invalid	PrWr	BusWr	Valid
Invalid	PrRd	BusRd	Valid

In all cases the written value goes to memory. Two allocation variants on Invalid + PrWr:

• Write-allocate: next state Valid; the written value is also cached
• Write-no-allocate: next state Invalid; not cached

Example

Initially x = 7 in main memory.

1. CPU1 reads x, caches it (Valid)
2. CPU3 reads x, caches it (Valid)
3. CPU3 writes x := 42. Goes to memory; CPU1 snoops BusWr and marks its copy Invalid
4. CPU1 reads x: miss, BusRd, fetches 42 from memory (Valid)
5. CPU2 reads x from memory (Valid)

Related

• Write-Back Cache
• Cache Coherency